LS1012ASN7HKA

The LS1012A processor features an advanced 64-bit Arm® Cortex®-A53 processor core with ECC-protected L1 and L2 cache memories along with datapath acceleration and network, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications.

• LS1012A contains one 64-bit Arm® Cortex®-A53 core processor
• One 16-bit DDR3L SDRAM memory controller
• Packet Forwarding Engine (PFE)
• Cryptography acceleration (SEC)
• Three SerDes lanes
• Ethernet Interfaces supported by PFE
• High-speed peripheral interfaces
• Additional peripheral interfaces
• QorIQ Platform’s Trust Architecture
• Debug supporting run control, data acquisition, highspeed trace, and performance/event monitoring
• Pre-boot loader (PBL) provides pre-boot initialization and RCW loading capabilities
• Single-source clocking solution enabling generation of core, platform, DDR, SerDes, and USB clocks from a single crystal oscillator