74LVC1G07GW,125

The 74LVC1G07GW,125 is a non-inverting Buffer with open-drain output. The open drain output can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3/5V devices. This feature allows the use of this device in a mixed 3.3 and 5V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

• High noise immunity
• CMOS low power consumption
• Direct interface with TTL levels
• Complies with JEDEC standard
• 5V Tolerant input/output for interfacing with 5V logic
• Latch-up performance exceeds 250mA
• Inputs accept voltages up to 5V