MTA4ATF51264HZ-3G2J1

MTA4ATF51264HZ-3G2J1 is a high-speed DDR4 SDRAM module that uses a DDR4 SDRAM device with two or four internal memory bank groups. The DDR4 SDRAM module benefits from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and eight corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins. The DDR4 module uses two sets of differential signals: DQS-t and DQS-c to capture data and CK-t and CK-c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.

• VDD = 1.20V (NOM), VPP = 2.5V (NOM), VDDSPD = 2.5V (NOM)
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR), data bus inversion (DBI) for data bus
• On-die VREFDQ generation and calibration
• On-board I2C serial presence-detect (SPD) EEPROM
• 8 internal banks; 2 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS
• 4GB module density, 512 Meg x 64 configuration, 25.6GB/s module bandwidth
• 260-pin DIMM package
• Commercial operating temperature range from 0 to 95°C