S70KS1282GABHV020

S70KS1282GABHV020 is a S70KS1282 128Mb 1.8V-only HYPERRAM™ self-refresh DRAM (PSRAM). The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ interface host. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed.

• Single-ended clock (CK) - 11 bus signals, chip select (CS#), 8-bit data bus (DQ[7:0])
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read data strobe
• The phase shifted clock is used to move the RWDS transition edge within the read data eye
• 200MHz maximum clock rate, DDR - transfers data on both edges of the clock
• Configurable output drive strength, hybrid sleep mode, deep power down
• 38-nm DRAM process technology - HYPERBUS™
• 200MHz speed
• 24-ball FBGA package
• Industrial plus (-40°C to +105°C) temperature range