S25FL256LAGMFM000

S25FL256LAGMFM000 is a 3.0V FL-L flash memory. The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (single I/O or SIO) is supported as well as optional two-bit (dual I/O or DIO) and four bit wide quad I/O (QIO) and quad peripheral interface (QPI) commands. In addition, there are double data rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page programming buffer that allows up to 256 bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.

• 256Mb density, 65nm floating gate process technology
• 133MHz speed, AEC-Q100 grade 1
• Supply voltage range from 2.7V to 3.6V, 6MB/s (50MHz) normal read speed
• 16.5MB/s (133MHz) fast read speed, 33MB/s (133MHz) dural read speed
• 66MB/s (133MHz) quad read speed, 66MB/s (66MHz) quad read speed (DDR)
• 256B program buffer size, individual and region protection or advanced sector protection
• Erase suspend/resume, program suspend/resume
• 20-year minimum data retention, min 100,000 program/erase cycles
• 256 Bytes page programming buffer, 3.0V FL-L flash memory
• Automotive temperature range from -40°C to +125°C, 16 pin SOIC package