S25FL128SAGMFMG00

S25FL128SAGMFMG00 is a FL-S flash non-volatile memory using MIRRORBIT™ technology - that stores two data bits in each memory array transistor, Eclipse architecture - that dramatically improves program and erase performance, 65-nm process lithography. This family of device connect to a host system via a SPI. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a page programming buffer that allows up to 128 words or 256 words to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called eXecute-in-Place or XIP.

• 128Mb density, 65-nm MIRRORBIT™ process technology, 133MHz speed
• 16-pin SO package type
• Temperature range from -40 to +125°C (automotive, AEC-Q100 grade 1)
• EHPLC, SO footprint with RESET#, uniform 64KB sectors with Hybrid 4KB sectors
• SPI with multi-I/O, SPI clock polarity and phase modes 0 and 3
• READ commands, Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR
• Common flash interface (CFI) data for configuration information, OTP array of 1024bytes
• Programming (1.5MBps), quad-input page programming (QPP) for slow clock systems
• Automatic ECC-internal hardware error correction code generation with single bit error correction
• Cycling endurance, 100000 program-erase cycles, minimum, data retention