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| 数量 | 价钱 (含税) |
|---|---|
| 1+ | CNY9.600 (CNY10.848) |
| 10+ | CNY6.310 (CNY7.1303) |
| 50+ | CNY6.240 (CNY7.0512) |
| 100+ | CNY6.160 (CNY6.9608) |
| 250+ | CNY6.090 (CNY6.8817) |
| 500+ | CNY6.010 (CNY6.7913) |
| 1000+ | CNY5.940 (CNY6.7122) |
| 2500+ | CNY5.860 (CNY6.6218) |
产品概述
The SN74LS112AN is a dual J-K Negative-Edge-Triggered Flip-Flop with clear and preset. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop can perform as toggle flip-flop by tying J and K high. The SN74S112A is characterized for operation from 0 to 70°C.
- Fully buffered to offer maximum isolation from external disturbance
- Quality and reliability
- Green product and no Sb/Br
技术规格
74LS112
15ns
8mA
DIP
下降沿
4.75V
74LS
0°C
-
-
JK
30MHz
DIP
16引脚
互补
5.25V
74112
70°C
-
No SVHC (27-Jun-2018)
法律与环境
进行最后一道重要生产流程所在的地区原产地:Malaysia
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书

